Semiconductor materials manufacturer Soitec (Euronext Paris:SOI) announced on Tuesday that it has entered into a strategic collaboration with Taiwan-based foundry Powerchip Semiconductor Manufacturing Corporation (PSMC) (TPE:6770) to advance ultra-thin Transistor Layer Transfer (TLT) technology for nanoscale 3D chip stacking.

Under the agreement Soitec will provide 300mm TLT-ready substrates with integrated release layers for use in a new wafer-level 3D stacking demonstration by PSMC. This marks the first public announcement of Soitec's TLT technology.

The innovation supports compact, high-performance and energy-efficient chip designs for applications such as smartphones, AI devices and autonomous systems. Soitec's TLT substrate enables high-speed transfer of ultra-thin transistor layers onto diverse wafers, a key requirement for heterogeneous integration.

The process supports vertical stacking of transistor layers, enabling advanced architectures like vertical field-effect transistors with backside power delivery networks. The technology combines Soitec's Smart Cut platform with infrared laser lift-off, allowing layer thicknesses from 5 nanometers to 1 micrometer without damaging devices.

This collaboration aligns with broader France-Taiwan initiatives in AI and semiconductor development.